Dr. Sakali Raghavendra Kumar is an Assistant Professor in the Department of Computer Science and Engineering at Shiv Nadar University Chennai. Prior to joining Shiv Nadar University Chennai, he served as an Assistant Professor in the Department of Computer Science and Engineering at Sri Sivasubramaniya Nadar (SSN) College of Engineering, Chennai. He received his Ph.D. (2021–2024) in Computer Science and Engineering from the Indian Institute of Information Technology, Design and Manufacturing (IIITDM) Kancheepuram, India. During his Ph.D., he worked as a Project Staff member on a Defence Research and Development Organisation (DRDO)-funded research project, contributing to the design and development of fault-tolerant hardware architectures for mission-critical applications.

His research interests include fault-tolerant and approximate adder and multiplier designs, as well as systolic-array multiplier architectures for machine learning (ML) and deep learning (DL) accelerators. His research focuses on designing approximate multiplier units for ML and DL accelerators, along with fault-tolerant arithmetic architectures. His current research aims to develop energy-efficient, high-performance multiplier architectures for image and video processing applications.

Work Experience: 

• July 2026 – Present, Assistant Professor, Department of Computer Science and Engineering, Shiv Nadar University Chennai, India. 
• August 2023 – June 2026, Assistant Professor, Department of Computer Science and Engineering, Sri Sivasubramaniya Nadar (SSN) College of Engineering, Chennai, India. 
• July 2019 – December 2020, Assistant Professor, Department of Computer Science and Engineering, SVR Engineering College, JNTUA, Nandyal, Andhra Pradesh, India. 
• July 2018 – July 2019, Assistant Professor, Department of Computer Science and Engineering, BIT Institute of Technology, JNTUA, Hindupur, Andhra Pradesh, India. 

Publications

List of Journal Publications

• Raghavendra Kumar Sakali, Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, and Noor Mahammad Sk. “Optimized Fault-Tolerant Adder Design Using Error Analysis.” Journal of Circuits, Systems and Computers (2022): 2350091, Vol. 32, No. 06. DOI: https://doi.org/10.1142/S0218126623500913
• Sakali Raghavendra Kumar, and Noor Mahammad “Intrinsic Based Self- Healing  Adder   Design    Using    Chromosome    Reconstruction Algorithm.” Journal of Electronic Testing 39, no. 1 (2023): 111-122. DOI: https://link.springer.com/article/10.1007/s10836-023-06050-1
• Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Noor Mahammad SK. “Preferential Fault-Tolerance Multiplier Design to Mitigate Soft Errors in FPGAs” was published in the Journal of VLSI Integration- Elsevier, Volume 93, Article No. 102068, Year 2023. DOI: https://doi.org/10.1016/j.vlsi.2023.102068
• Raghavendra Kumar Sakali, Noor Mahammad Sk, “Fault-tolerant multiplier using self-healing technique”, Microelectronics Reliability, 160, 2024 and page no. 115458. DOI: https://doi.org/10.1016/j.microrel.2024.115458
• Pankaj Kumar Raghuwanshi, Ajay Kumar Reddy Poreddy, Sakali Raghavendra Kumar, Balasubramanyam Appina, “An Unsupervised Stereoscopic Image Quality Prediction Model Using Perceptual and Statistical Features of Scene Attributes” IEEE Transactions on Instrumentation and Measurement, 2025. DOI: 1109/TIM.2025.3619656

List of Conference Publications

• Sakali Raghavendra Kumar, Noor Mahammad Sk, Balasubramanian P, G. Venkat “Novel Embryonic Adder Architecture with Uni-Cellular Self Check Unit” is proceedings in 2^nd International Conference on Emerging Trends in Engineering 2023, Atlantis Press. DOI: https://doi.org/10.2991/978-94-6463-252-1_93
• Sakali Raghavendra Kumar, Sreehari Veeramachaneni, Sk Noor Mahammad, Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems, 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), January and 2024, Kolkata, India. DOI: https://doi.org/10.1109/VLSID60093.2024.00120
• S. Deepanjali, Noor Mahammad Sk and Sakali Raghavendra Kumar, Fault Resilient Micro-Coded Control Unit for Space-Based Digital Systems,”2024 28th International Symposium on VLSI Design and Test (VDAT), Vellore, India, 2024, pp. 1-6. DOI: https://doi.org/10.1109/VDAT63601.2024.10705726
• S. Raghavendra Kumar and Sk. Noor Mahammad, “Preferential Fault-Tolerant Based TF32 Floating Point Adder for Mission Critical Systems,” in December 2024 the 33^rd IEEE Asian Test Symposium (ATS 2024), Ahmedabad, India, 2024. DOI: https://doi.org/10.1109/ATS64447.2024.10915484

Area of Research

• Computer Architecture
• Reconfigurable Computing
• Fault-Tolerant Adder and Multiplier
• Approximate Adder and Multiplier

Links

• Personal Website: https://raghavendrak29.github.io/SRK_Profle/
• Google Scholar: https://scholar.google.com/citations?user=8SVnUbwAAAAJ&hl=en