SOI MUMPS Microfabrication Process: Translating Design to Prototype
Are you interested in building a skill-set that will enable you to quickly translate your MEMS design to foundry ready design for rapid prototyping? If your answer is yes, this workshop is for you
Jointly Organises A Two-day Hands-on Workshop On SOI MUMPS Microfabrication Process: Translating Design to Prototype March 24-25 , 2023
This will be a hands-on familiarization workshop on fabrication process steps, design rules and multilayer mask generation for translating a design to its prototype using the Silicon-on-Insulator (SOI) Multiuser MEMS (SOI-MUMPS.) process. The participants will be trained on how to build a prototype of a device, by using external foundry services. The training will start from (i) understanding the design rules of the foundry, (ii) checking the device design for compliance with these rules (DRC), (iii) running coupled Multiphysics simulation to extract expected performance characteristics (iv) preparation of masks and (v) virtual prototyping of each individual process step to build a 3 D model of the resulting structure using Intellifab and Intellisuite MEMS CAD tool. They will also learn the conventions of labeling the mask files and how to prepare reports for the foundry and relevant stakeholders. At the end of the session, the participants can submit a report to build a device of their interest or from one among those suggested, in the required format. The best design will be considered for upcoming fabrication runs.

Who can participate: UG/PG students/Research Scholars/Faculty
Workshop Registration Fees: Rs 550/ –
With Boarding & Lodging For Students (March 24-25,2023) : Rs 850/-
With Boarding & Lodging For Teachers (March 24-25,2023) : Rs 1200/-
Contact: Dr Prita Nair, SNU Chennai pritanair@snuchennai.edu.in

Program Schedule

Day 1: 24 March, 2023 Friday,
Venue: Academic Block 1, Shiv Nadar University, Chennai
8:00  Reception Desk Opens
8:30  Introduction to SOI and SOI MUMPS process -Illustration with an example
9:30  DRC rules for translation from design to Fab -INFAB and MEMSCAP SOI MUMPS Process
10:30  Tea Break
10:45  Checking for dimensional compliance of the example device
11:30  Introduction to Intellisense : Hands-on session on Building 3D model in Intellisuite
13:00  Lunch
14:00  Multiphysics Hands-on Session on Simulation of device performance in Intellisuite
(from 3D model)
15:15  Distribution of Assignments: To spot DRC errors and build 3D models
15:30 Tea

Day 2: 25 March, 2023 Saturday
Venue: Computer Lab, Academic Block 1, Shiv Nadar University, Chennai
08:30 Mask generation for SOI MUMPs process.
10:30 Tea Break
10:45 -Intellifab for virtual prototyping using the masks
13:00 Lunch
14:00 Report preparation giving top and cross-sectional views
15: 00 Concluding Session: Certificate Distribution & Feedback
15:30 Tea & Dispersal